在cubeide中，用cubemx产生stm32g474re LL库的初始代码中，ADC1和ADC2配成独立工作，但是在MX_ADC2_Init(void)中，这两句是错的  LL_ADC_DisableDeepPowerDown(ADC1);
5 R- D; N  v* n: j/ P# A; e, a4 l  u  LL_ADC_EnableInternalRegulator(ADC1);
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将导致ADC2不供电，无法工作，每次都要手工改过来才能正常工作。


  * @brief ADC2 Initialization Function
  * @param None
! z; k$ m. o3 \$ @  * @retval None
  */
static void MX_ADC2_Init(void)
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2 A1 h9 H$ w, N. N  /* USER CODE BEGIN ADC2_Init 0 */
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1 I$ C; L' z5 _6 |3 I: ]- F/ N  /* USER CODE END ADC2_Init 0 */
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  LL_ADC_InitTypeDef ADC_InitStruct = {0};
6 z3 r7 w, |0 c4 D6 ]( u  LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0};

  /* Peripheral clock enable */
; f7 G1 e' ]7 `, _3 A0 U  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC12);

& g8 K7 p- z# x# T" d' W, F9 `1 t; J  /* ADC2 DMA Init */
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  /* ADC2 Init */
: x0 J; j+ z) G, L  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_ADC2);

! l# Z( e& Q3 m/ p0 |  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
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  LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PRIORITY_MEDIUM);

  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MODE_NORMAL);
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  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PERIPH_NOINCREMENT);

' x; M/ k) ~5 ^- q  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MEMORY_INCREMENT);
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/ K+ h. ?! e2 n8 ^  LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_PDATAALIGN_WORD);
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: K8 W# {+ X- _# o; D7 Z  l  LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_1, LL_DMA_MDATAALIGN_HALFWORD);

2 H) {- y, h8 Q1 j5 S- b' |  /* USER CODE BEGIN ADC2_Init 1 */

  /* USER CODE END ADC2_Init 1 */
  /** Common config
  */
% O6 ~5 K+ u- q& j: r9 d% M  `  ADC_InitStruct.Resolution = LL_ADC_RESOLUTION_12B;
8 A7 ?% P1 u- d/ c, O/ k6 x  ADC_InitStruct.DataAlignment = LL_ADC_DATA_ALIGN_LEFT;
$ Y/ K+ R6 ~* N) o6 L  ADC_InitStruct.LowPowerMode = LL_ADC_LP_MODE_NONE;
' U" c$ `2 B( U+ j0 e" H* S% j  LL_ADC_Init(ADC2, &ADC_InitStruct);
* {1 W# ^- B. T3 U  ADC_REG_InitStruct.TriggerSource = LL_ADC_REG_TRIG_EXT_TIM8_TRGO;
  ADC_REG_InitStruct.SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
$ [! w; Z. _; ~4 v) I4 p" }  ADC_REG_InitStruct.SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
/ @# \; I$ W: P- _  ADC_REG_InitStruct.ContinuousMode = LL_ADC_REG_CONV_SINGLE;
  ADC_REG_InitStruct.DMATransfer = LL_ADC_REG_DMA_TRANSFER_UNLIMITED;
+ [- V7 X- D  e: E. J% o& e% b3 z  ADC_REG_InitStruct.Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
9 x% v6 ]+ X; b  LL_ADC_REG_Init(ADC2, &ADC_REG_InitStruct);
  LL_ADC_SetGainCompensation(ADC2, 0);
0 ~9 c, C7 M# a8 U) F1 `  LL_ADC_SetOverSamplingScope(ADC2, LL_ADC_OVS_DISABLE);
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  /* Disable ADC deep power down (enabled by default after reset state) */
  LL_ADC_DisableDeepPowerDown(ADC1);
& p  s' k) f6 F) J. }  /* Enable ADC internal voltage regulator */
5 x: r/ c1 k0 B4 ^, J1 q" v: k  LL_ADC_EnableInternalRegulator(ADC1);
  /* Delay for ADC internal voltage regulator stabilization. */
8 U7 B1 {3 H- \( t& s  /* Compute number of CPU cycles to wait for, from delay in us. */
  /* Note: Variable divided by 2 to compensate partially */
  /* CPU processing cycles (depends on compilation optimization). */
  /* Note: If system core clock frequency is below 200kHz, wait time */
6 F% A, j7 c$ `  /* is only a few CPU processing cycles. */

& N( r- Z: @4 V/ v: C1 i( d  uint32_t wait_loop_index;
  wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (100000 * 2))) / 10);
2 A! y- Y! X6 {/ t* f# |* ?' A2 y2 ]  while(wait_loop_index != 0)
  {
  P3 C- P; [4 n" @; j! o; Z    wait_loop_index--;
  }
  LL_ADC_REG_SetTriggerEdge(ADC2, LL_ADC_REG_TRIG_EXT_RISING);
# q# a. K3 u0 ]! j+ D$ X/ I* b# J  /** Configure Regular Channel
3 i  J$ M5 V+ p  J% U  */
. w7 W5 q  i! K3 W: o  LL_ADC_REG_SetSequencerRanks(ADC2, LL_ADC_REG_RANK_1, LL_ADC_CHANNEL_VOPAMP3_ADC2);
  LL_ADC_SetChannelSamplingTime(ADC2, LL_ADC_CHANNEL_VOPAMP3_ADC2, LL_ADC_SAMPLINGTIME_6CYCLES_5);
  LL_ADC_SetChannelSingleDiff(ADC2, LL_ADC_CHANNEL_VOPAMP3_ADC2, LL_ADC_SINGLE_ENDED);
  LL_ADC_SetOffset(ADC2, LL_ADC_OFFSET_1, LL_ADC_CHANNEL_VOPAMP3_ADC2, 0);
; u3 o7 u4 H3 n9 F  LL_ADC_SetOffsetSign(ADC2, LL_ADC_OFFSET_1, LL_ADC_OFFSET_SIGN_NEGATIVE);
  LL_ADC_SetOffsetSaturation(ADC2, LL_ADC_OFFSET_1, LL_ADC_OFFSET_SATURATION_DISABLE);
# B! y( f: m2 {  ~* c9 U. [7 g& Z* `  /* USER CODE BEGIN ADC2_Init 2 */
  LL_ADC_StartCalibration(ADC2, LL_ADC_SINGLE_ENDED);
' J9 i1 g# O( G0 ^7 R  while (LL_ADC_IsCalibrationOnGoing(ADC2) != 0)  { };

  wait_loop_index = (ADC_DELAY_CALIB_ENABLE_CPU_CYCLES >> 1);
/ o! b2 E7 @5 N/ o! n  while(wait_loop_index != 0)
  {
    wait_loop_index--;
  }
0 W, N6 F" v1 w' v1 a+ R  /* Enable ADC */
  LL_ADC_Enable(ADC2);

& j/ k4 m1 T0 T& E4 Y  /* Poll for ADC ready to convert */
  while (LL_ADC_IsActiveFlag_ADRDY(ADC2) == 0)         { };
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  /* USER CODE END ADC2_Init 2 */

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