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请大家帮助M48T58时钟存储芯片怎么样设置编程，用C编写，寄存器。下面是截取的技术文档资料，请大家帮忙看下怎么样编写程序设置时钟芯片，可下载PDF文档 Setting the clock Bit D7 of the Control register (1FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER® registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 5). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. The bits marked as '0' in Table 5 on page 16 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. After the WRITE Bit is reset, the next clock update will occur within one second. See the Application Note AN923 “TIMEKEEPER Rolling Into the 21st Century” for information on Century Rollover. Table 5. Register map Keys: S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to '0' BLE = Battery Low Enable Bit BL = Battery Low Bit (Read only) CEB = Century Enable Bit CB = Century Bit Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to CEB. 6.4 Calibrating the Clock The M48T58/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T58/Y improves to better than +1/–2 ppm at 25°C. The oscillation rate of any crystal changes with temperature (see Figure 8 on page 18). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M48T58/Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9 on page 18. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register 1FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit Address Data Function/Range D7 D6 D5 D4 D3 D2 D1 D0 BCD Format 1FFFh 10 Years Year Year 00-99 1FFEh 0 0 0 10 M Month Month 01-12 1FFDh BLE BL 10 Date Date Date 01-31 1FFCh 0 FT CEB CB 0 Day Century/Day 0-1/1-7 1FFBh 0 0 10 Hours Hours Hours 00-23 1FFAh 0 10 Minutes Minutes Minutes 00-59 1FF9h ST 10 Seconds Seconds Seconds 00-59 1FF8h W R S Calibration Control |
M48T58,datasheet.pdf
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谢谢；初始化，初始化需要电源低标志位置1电压检测位置1，