问题:在使用定时器输出PWM时,假如此时关闭PWM的输出,其IO口会出现高低电平交替出现的情况!1.代码设置:TIM2->CCER2寄存器设置的是输出使能和输出有效电平为低电平;
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U! e: c1 `+ b, _- /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity(low) */8 [& T7 G7 ^4 D$ V. x$ c
- TIM2->CCER2 &= (uint8_t)(~( TIM2_CCER2_CC3E | TIM2_CCER2_CC3P));- H; M1 s* O' x" D9 a' }% F1 B
- /* Set the Output State & Set the Output Polarity */
" E: a% q3 C" C1 }& E' k+ a& t; R: R - TIM2->CCER2 |= (uint8_t)((uint8_t)(0x11 & TIM2_CCER2_CC3E) | (uint8_t)(0x02 & TIM2_CCER2_CC3P));
3 z& A* Z$ w' K" r2 n6 @0 V9 ~# m5 r - /* Reset the Output Compare Bits & Set the Output Compare Mode(PWM1) */3 _7 t4 ^' f6 F3 C/ ~, C
- TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) |<font color="#ff0000"> (uint8_t)0x60</font>);
复制代码 2.停止输出PWN:先使能定时器,然后强制输出为有效电平;
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" v) b+ H4 A7 D5 u% Y- /* Disable timer2 */5 F9 X$ G5 }5 R5 `- U3 J
- TIM2->CR1 &= (uint8_t)(~TIM2_CR1_CEN); ( K D; _; }. q) G, j* B
- /* Reset the OCM Bits & Configure the Forced output Mode */
1 r2 w+ H6 f3 H8 S8 ` - TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) | <font color="#ff0000">(uint8_t)0x50</font>);
复制代码 3.重新启动定时器输出PWM:重新配置位输出PWM1模式,启动定时器! K; H- k3 H, {4 t9 L
- /* Reset the OCM Bits & Configure the Forced output Mode */
q/ L" z8 I# v( Q9 m* n8 M9 r Z) a - TIM2->CCMR3 = (uint8_t)((uint8_t)(TIM2->CCMR3 & (uint8_t)(~TIM2_CCMR_OCM)) | <font color="#ff0000">(uint8_t)0x60</font>);
! a/ N# Y2 c- `- u% E6 E k0 K - TIM2->CR1 |= (uint8_t)TIM2_CR1_CEN; //产生pwm
复制代码 4.至于上面红色的设置关键字:' W; S, `; j) h5 a1 f7 r/ _$ |
来自于stm8s参考手册TIMx_CCMR1+ N% |0 c" c& S
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